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Rev 0; 7/04
Low-Voltage SPI/3-Wire RTCs with Trickle Charger
General Description
The low-voltage serial-peripheral interface (SPITM) DS1390/DS1391 and the low-voltage 3-wire DS1392/ DS1393 real-time clocks (RTCs) are clocks/calendars that provide hundredths of a second, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. One programmable time-of-day alarm is provided. A temperature-compensated voltage reference monitors the status of VCC and automatically switches to the backup supply if a power failure is detected. On the DS1390, a single open-drain output provides a CPU interrupt or a square wave at one of four selectable frequencies. The DS1391 replaces the SQW/INT pin with a RST output/debounced input. The DS1390 and DS1391 are programmed serially through an SPI-compatible, bidirectional bus. The DS1392 and DS1393 communicate over a 3-wire serial bus, and the extra pin is used for either a separate interrupt pin or a RST output/debounced input. All four devices are available in a 10-pin SOP package, and are rated over the industrial temperature range.
Features
Real-Time Clock Counts Hundredths of Seconds, Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap-Year Compensation Valid Up to 2100 Output Pin Configurable as Interrupt or Square Wave with Programmable Frequency of 32.768kHz, 8.192kHz, 4.096kHz, or 1Hz (DS1390/DS1393 Only) One Time-of-Day Alarm Power-Fail Detect and Switch Circuitry Reset Output/Debounced Input (DS1391/DS1393) Separate SQW and INT Output (DS1392) Trickle-Charge Capability SPI Supports Modes 1 and 3 (DS1390/DS1391) 3-Wire Interface (DS1392/DS1393) 4MHz at 3.0V and 3.3V 1MHz at 1.8V Three Operating Voltages: 1.8V 5%, 3.0V 10%, and 2.97 to 5.5V Industrial Temperature Range: -40C to +85C Underwriters Laboratory (UL) Recognized
DS1390/DS1391/DS1392/DS1393
Applications
Hand-Held Devices GPS/Telematics Devices Embedded Time Stamping Medical Devices
PART
Ordering Information
PINTOP MARK PACKAGE DS1390U-18 -40C to +85C 10 SOP DS1390 rr-18 DS1390U-3 -40C to +85C 10 SOP DS1390 rr-3 DS1390U-33 -40C to +85C 10 SOP DS1390 rr-33 DS1391U-18 -40C to +85C 10 SOP DS1391 rr-18 DS1391U-3 -40C to +85C 10 SOP DS1391 rr-3 DS1391U-33 -40C to +85C 10 SOP DS1391 rr-33 DS1392U-18 -40C to +85C 10 SOP DS1393 rr-18 DS1392U-3 -40C to +85C 10 SOP DS1392 rr-3 DS1392U-33 -40C to +85C 10 SOP DS1392 rr-33 DS1393U-18 -40C to +85C 10 SOP DS1393 rr-18 DS1393U-3 -40C to +85C 10 SOP DS1393 rr-3 DS1393U-33 -40C to +85C 10 SOP DS1393 rr-33 Where "rr" is a revision code on the second line of the top mark. TEMP RANGE
Typical Operating Circuits and Pin Configurations appear at end of the data sheet.
SPI is a trademark of Motorola, Inc. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Voltage Range on Inputs Relative to Ground ...............................................-0.3V to (VCC + 0.3V) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at nominal supply voltage and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage (Note 2) SYMBOL DS139x-33 VCC DS139x-3 DS139x-18 Logic 1 Logic 0 Supply Voltage, Pullup SQW/INT, SQW, INT, VCC = 0V VBACKUP Voltage (Note 2) VIH VIL VPU (Note 2) (Note 2) (Note 2) -33 VBACKUP -3 -18 -33 Power-Fail Voltage (Note 2) VPF R1 Trickle-Charge Current-Limiting Resistors Input Leakage I/O Leakage RST Pin I/O Leakage DOUT Logic 1 Output DOUT Logic 0 Output Logic 0 Output (DS1390/DS1393 SQW/INT; DS1392 SQW, INT; DS1391/DS1393 RST) VCC Active Supply Current (Note 10) R2 R3 ILI ILO ILORST IOHDOUT IOHDOUT -3 -18 (Notes 3, 4) (Notes 3, 5) (Notes 3, 6) (Note 7) (Note 8) (Note 9) -33, -3 (VOH = 0.85 x VCC) -18 (VOH = 0.80 x VCC) -33, -3 (VOL = 0.15 x VCC) -18 (VOL = 0.20 x VCC) VCC > 1.71V; VOL = 0.4V IOLSIR 1.3V < VCC < 1.71V; VOL = 0.4V -33 ICCA -3 -18 250 2 2 500 A mA A -1 -1 -200 1.3 1.3 1.3 2.70 2.45 1.51 CONDITIONS MIN 2.97 2.7 1.71 0.7 x VCC -0.3 TYP 3.3 3.0 1.8 MAX 5.50 3.3 1.89 VCC + 0.5 +0.3 x VCC 5.5 3.0 VCC(MAX) 3.0 3.0 2.88 2.6 1.6 250 2000 4000 +1 +1 +10 -1 0.750 3 2 3.0 A A A mA mA mA 3.7 3.7 2.97 2.70 1.71 V V V V V UNITS V
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted. Typical values are at nominal supply voltage and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER VCC Standby Current (Note 11) VBACKUP Leakage Current (VBACKUP = 3.7V, VCC = VCC(MAX)) SYMBOL -33 ICCS -3 -18 IBACKUPLKG CONDITIONS MIN TYP 115 80 60 15 MAX 175 125 100 100 nA UNITS A
DS1390/DS1391/DS1392/DS1393
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBACKUP = 3.7V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER VBACKUP Current OSC On, SQW Off VBACKUP Current OSC On, SQW On (32kHz) VBACKUP Current OSC On, SQW On, VBACKUP = 3.0V, TA = +25C VBACKUP Current, OSC Off (Data Retention) SYMBOL IBACKUP1 IBACKUP2 (Note 12) (Note 12) CONDITIONS MIN TYP 500 600 MAX 1000 1150 UNITS nA nA
IBACKUP3
(Note 12)
600
1000
nA
IBACKUPDR (Note 12)
25
100
nA
AC ELECTRICAL CHARACTERISTICS--SPI INTERFACE
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER SCLK Frequency (Note 13) Data to SCLK Setup SCLK to Data Hold SCLK to Data Valid (Notes 13, 14, 15) SCLK Low Time (Note 13) SCLK High Time (Note 13) SCLK Rise and Fall CS to SCLK Setup (Note 13) SCLK to CS Hold (Note 13) CS Inactive Time (Note 13) CS to Output High Impedance SYMBOL fSCLK tDC tCDH tCDD tCL tCH tR, tF tCC tCCH tCWH tCDZ 2.7V VCC . 5.5V 1.71V VCC 1.89V (Notes 13, 14) 400 100 400 500 40 CONDITION 2.7V VCC 5.5V 1.71V VCC 1.89V (Notes 13, 14) (Notes 13, 14) 2.7V VCC 5.5V 1.71V VCC 1.89V 2.7V VCC . 5.5V 1.71V VCC 1.89V 2.7V VCC 5.5V 1.71V VCC 1.89V 110 400 110 400 200 30 30 80 160 MIN TYP MAX 4 1 UNITS MHz ns ns ns ns ns ns ns ns ns ns
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
CS
tCC SCLK
tR
tF
tCL tCDH DIN tDC W/R A6
tCH tCDD A0
tCDZ
DOUT D7 D0
WRITE ADDRESS BYTE NOTE: SCLK CAN BE EITHER POLARITY, SHOWN FOR CPOL = 1.
READ DATA BYTE
Figure 1. Timing Diagram--SPI Read Transfer
CS SCLK tCC tR tCL tF
tCWH tCCH
DIN
tDC W/R
tCDH
tCH
A6
A0
D7
D0
WRITE ADDRESS BYTE
WRITE DATA BYTE
Figure 2. Timing Diagram--SPI Write Transfer
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
AC ELECTRICAL CHARACTERISTICS--3-WIRE INTERFACE
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C.) (Note 1) (Figures 3, 4)
PARAMETER SCLK Frequency (Note 13) Data to SCLK Setup SCLK to Data Hold SCLK to Data Valid (Notes 13, 14, 15) SCLK Low Time (Note 13) SCLK High Time (Note 13) SCLK Rise and Fall CS to SCLK Setup SCLK to CS Hold CS Inactive Time (Note 13) CS to Output High Impedance SYMBOL fSCLK tDC tCDH tCDD tCL tCH tR, tF tCC tCCH tCWH tCDZ (Note 13) (Note 13) 2.7V VCC 5.5V 1.71V VCC 1.89V (Note 13, 14) 400 100 400 500 40 CONDITION 2.7V VCC 5.5V 1.71V VCC 1.89V (Notes 13, 14) (Notes 13, 14) 2.7V VCC 5.5V 1.71V VCC 1.89V 2.7V VCC 5.5V 1.71V VCC 1.89V 2.7V VCC 5.5V 1.71V VCC 1.89V 110 400 110 400 200 30 30 80 160 MIN TYP MAX 4 1 UNITS MHz ns ns ns ns ns ns ns ns ns ns
DS1390/DS1391/DS1392/DS1393
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Pushbutton Debounce Reset Active Time Oscillator Stop Flag (OSF) Delay SYMBOL PBDB tRST tOSF (Note 16) CONDITIONS MIN TYP 160 160 100 MAX 200 200 UNITS ms ms ms
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
CE
tCC
tR
tF
SCLK
tCL tCDH tDC
I/O
tCH tCDD
tCDZ
A0
A1
R/W
D0
D7
WRITE ADDRESS BYTE
READ DATA BYTE
Figure 3. Timing Diagram--3-Wire Read Transfer
tCWH CE tCC SCLK tCL tCDH tDC I/O A0 A1 R/W D0 D7 tCH tR tF tCCH
WRITE ADDRESS BYTE
WRITE DATA BYTE
Figure 4. Timing Diagram--3-Wire Write Transfer
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40C to +85C) (Figures 5, 6)
PARAMETER VCC Detect to Recognize Inputs (VCC Rising) VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tRST tF tR (Note 17) 300 0 CONDITIONS MIN TYP 160 MAX 200 UNITS ms s s
DS1390/DS1391/DS1392/DS1393
VCC VPF(MAX) VPF(MIN) tF
VPF
VPF
tR tRPU tRST
RST
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-IMPEDANCE OUTPUTS VALID VALID
Figure 5. Power-Up/Down Timing
RST
PBDB
tRST
Figure 6. Pushbutton Reset Timing
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
CAPACITANCE
(TA = +25C)
PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins (High Impedance) SYMBOL CIN CIO CONDITIONS MIN TYP MAX 10 10 UNITS pF pF
WARNING:
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17:
Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. The use of the 250 trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Use of the diode is not recommended for VCC < 3.0V. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A5h. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A6h. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A7h. SCLK, DIN, CS on DS1390/DS1391; SCLK, and CE on DS1392/DS1393. DOUT, SQW/INT (DS1390/DS1393), SQW, and INT (DS1392). The RST pin has an internal 50k (typ) pullup resistor to VCC. ICCA--SCLK clocking at max frequency = 4MHz for 3V and 3.3V versions; 1MHz for 1.8V version; RST (DS1391/DS1393) inactive. Outputs are open. Specified with bus inactive. Measured with a 32.768kHz crystal attached to X1 and X2. Typical values measured at +25C and 3.0VBACKUP. With 50pF load. Measured at VIH = 0.7 x VDD or VIL = 0.2 x VDD, 10ns rise/fall times. Measured at VOH = 0.7 x VDD or VOL = 0.2 x VDD. Measured from the 50% point of SCLK to the VOH minimum of SDO. The parameter tOSF is the time that the oscillator must be stopped for the OSF flag to be set over the voltage range of 0 VCC VCC(MAX) and 1.3V VBAT 5.5V. This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is added to this delay.
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
IBACKUP vs. VBACKUP, BBSQ1 = 0
VCC= 0 550 SUPPLY CURRENT (nA) 500 450 400 350 300 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 VBACKUP (V)
DS1390 TOC01
IBACKUP vs. VBACKUP, BBSQ1 = 1
1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 VBACKUP (V) VCC = 0V
DS1390 toc02
600
SUPPLY CURRENT (nA)
1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
IBACKUP vs. TEMPERATURE VBACKUP = 3.0V
DS1390 toc03
OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
DS1390 toc04
600 VCC = 0V 550 SUPPLY CURRENT (nA) 500 450 400 350 300 250 -40 -20 0 20 40 60 80 TEMPERATURE (C)
32768.00
32767.95 FREQUENCY (Hz)
32767.90
32767.85
32767.80 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 SUPPLY (V)
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Pin Description
PIN DS1390 DS1391 DS1392 DS1393 1 1 1 1 NAME FUNCTION Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a 6pF specified load capacitance (CL). Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. DC Backup Power Input for Primary Cell. This pin is a rechargeable battery/super cap or a secondary supply. UL recognized to ensure against reverse charging current when used with a lithium battery. SPI Chip-Select Input. This pin is used to select or deselect the part. Chip Enable for 3-Wire Interface Ground SPI Data Input. This pin is used to shift address and data into the part. Interrupt Output. This pin is used to output the interrupt signal, if enabled by the control register. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, INT functions when the device is powered by either VCC or VBAT. Reset. This active-low, open-drain output indicates the status of VCC relative to the VPF specification. As Vcc falls below VPF, the RST pin is driven low. When Vcc exceeds VPF, for tRST, the RST pin is driven high impedance. This pin is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. This pin has an internal, 50k (typ) pullup resistor to VCC. No external pullup resistors should be connected. If the crystal oscillator is disabled, the startup time of the oscillator is added to the tRST delay. SPI Data Output. Data is output on this pin when the part is in read mode. CMOS push-pull driver. Input/Output for 3-Wire Interface. CMOS push-pull driver. Serial Clock Input. This pin is used to control the timing of data into and out of the part. Square-Wave/Interrupt Output. This pin is used to output the programmable square wave or interrupt signal. When enabled by setting the ESQW bit to logic 1, the SQW/INT pin outputs one of four frequencies: 32.768kHz, 8.192kHz, 4.096kHz, or 1Hz. This pin is open drain and requires an external pullup resistor. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, SQW/INT functions when the device is powered by either VCC or VBAT. Square-Wave Output. This pin is open drain and requires an external pullup resistor. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, SQW functions when the device is powered by either VCC or VBAT. DC Power Pin for Primary Power Supply
X1
2
2
2
2
X2
3 4 -- 5 6
3 4 -- 5 6
3 -- 4 5 --
3 -- 4 5 --
VBACKUP CS CE GND DIN
--
--
6
--
INT
--
9
--
6
RST
7 -- 8
7 -- 8
-- 7 8
-- 7 8
DOUT I/O SCLK
9
--
--
9
SQW/INT
--
--
9
--
SQW
10
10
10
10
VCC
10
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
Functional Diagram
DS1390/DS1391/DS1392/DS1393
X1
X2
32,768Hz CRYSTAL OSCILLATOR
HUNDREDTHS-OFSECONDS GENERATOR
VCC GND VBACKUP
VCC LEVEL DETECT, POWER SWITCH, WRITE PROTECT, TRICKLE CHARGER REAL-TIME CLOCK WITH HUNDREDTHS OF SECONDS
SQUARE-WAVE RATE SELECTOR, INT, MUX, RST OUTPUT
SQW/INT (DS1390/93) RST (DS1391/93) SQW (DS1392)
(DS1390/91) CS (DS1392/93) (CE) SCLK (DS1390/91) DIN (DS1390/91) DOUT (DS1392/93) I/O BUS INTERFACE CONTROL/STATUS REGISTERS TRICKLE REGISTER ALARM REGISTERS
DS1390/DS1391/ DS1392/DS1393
Detailed Description
The DS1390/DS1391/DS1392/DS1393 RTCs are lowpower clocks/calendars with alarms. Address and data are transferred serially through a 4-wire SPI interface for the DS1390 and DS1391 and through a 3-wire interface for the DS1392 and DS1393. The clocks/calendars provide hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The alarm functions are performed off all timekeeping registers, allowing the user to set high resolution alarms. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clocks operate in either the 24hour or 12-hour format with an AM/PM indicator. All four devices have a built-in temperature-compensated voltage reference that detects power failures and automati-
cally switches to the battery supply. Additionally, the devices can provide trickle charging of the backup voltage source, with selectable charging resistance and diode voltage drops.
Operation
The DS1390/DS1391 operate as a slave device on the SPI serial bus. The DS1392/DS1393 operate using a 3-wire synchronous serial bus. Access is obtained by selecting the part by the CS pin (CE on DS1392/ DS1393) and clocking data into/out of the part using the SCLK and DIN/DOUT pins (I/O on DS1392/ DS1393). Multiple-byte transfers are supported within one CS low period (see the SPI Serial-Data Bus section). The devices are fully accessible and data can be written and read when V CC is greater than V PF .
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to V BACKUP when V CC drops below V PF . If V PF is greater than VBACKUP, the device power is switched from V CC to V BACKUP when V CC drops below V BACKUP . The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. See the Functional Diagram for the main elements of these serial RTCs.
Oscillator Circuit
All four devices use an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal, and Figure 7 shows a functional schematic of the oscillator circuit. If a crystal is used with the specified characteristics, the startup time is usually less than one second.
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 8 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 6 MIN TYP 32.768 55 MAX UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
LOCAL GROUND PLANE (LAYER 2)
COUNTDOWN CHAIN
X1 CRYSTAL X2
C L1
C L2
RTC REGISTERS
DS139x
X1 X2
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE.
GND
CRYSTAL
Figure 7. Oscillator Circuit Showing Internal Bias Network
Figure 8. Layout Example
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
Address Map
Table 2 shows the address map for the DS1390- DS1393 RTC and RAM registers. The RTC registers are located in address locations 00h to 0Fh in read mode, and 80h to 8Fh in write mode. During a multibyte access, when the address pointer reaches 0Fh, it wraps around to location 00h. On the falling edge of the CS pin (DS1390/DS1391) or the rising edge of CE (DS1392/DS1393), the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers if the main registers update during a read. To avoid rollover issues when writing to the time and date registers, all registers should be written before the hundredths-of-seconds registers reaches 99 (BCD).
DS1390/DS1391/DS1392/DS1393
Table 2. Address Map
WRITE READ ADDRESS ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah AM1 AM2 0 0 0 0 0 Century 12/24 0 0 0 10 Year Tenths of Seconds 10 Seconds 10 Minutes AM/PM 10 Hour 8Ch 0Ch AM4 DY/DT 0 8Dh 8Eh 8Fh 0Dh 0Eh 0Fh EOSC OSF TCS3 0 0 0 TCS2 10 Date BBSQI X BBSQI 0 TCS1 RS2 X RS2 0 TCS0 RS1 X RS1 0 DS1 Day Date INTCN X ESQW 0 DS0 0 0 0 0 ROUT1 AIE X AIE AF ROUT0 Status Trickle Charger Control Alarm Day Alarm Date 1-7 BCD 1-31 BCD DS1390/93 DS1391 DS1392 -- -- 10 Hour BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Hundredths of Seconds Seconds Minutes Hours Day Date Month Year Hundredths of Seconds Seconds Minutes Day Date Month/ Century Year Alarm Hundredths of Seconds Alarm Alarm RANGE 0-99 BCD 00-59 BCD 00-59 BCD 1-12 +AM/PM 00-23 BCD 1-7 BCD 01-31 BCD 01-12 + Century BCD 00-99 BCD 0-99 BCD 00-59 BCD 00-59 BCD 1-12 + AM/PM 00-23 BCD
Tenths of Seconds 10 Seconds 10 Minutes AM/PM 10 Hour 0 10 Date 0 10 Month 10 Hour 0 0
Hundredths of Seconds Seconds Minutes Hour
8Bh
0Bh
AM3
12/24
Hour
Alarm Hours
Note: Unless otherwise specified, the state of the registers is not defined when power (VCC and VBACKUP) is first applied. X = General-purpose read/write bit. 0 = Always reads as zero. ____________________________________________________________________ 13
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Hundredths-of-Seconds Generator
The hundredths-of-seconds generator circuit shown in the functional diagram is a state machine that divides the incoming frequency (4096Hz) by 41 for 24 cycles and 40 for one cycle. This produces a 100Hz output that is slightly off during the short term, and is exactly correct every 250ms. The divide ratio is given by: Ratio = [41 x 24 + 40 x 1] / 25 = 40.96 Thus, the long-term average frequency output is exactly the desired 100Hz. register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). Changing the 12/24-hour modeselect bit requires that the hours data be re-entered, including the alarm register (if used). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00.
Alarms
All four devices contain one time-of-day/date alarm. Writing to registers 88h through 8Ch sets the alarm. The alarm can be programmed (by the alarm enable and INTCN bits of the control register) to activate the SQW/INT or INT output on an alarm-match condition. The alarm can activate the SQW/INT or INT output while the device is running from V BACKUP if BBSQI is enabled. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 3). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 3 shows the possible settings. Configurations not listed in the table result in illogical operation.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. See Table 2 for the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day-of-week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. The DS1390-DS1393 can run in either 12-hour or 24-hour mode. Bit 6 of the hours
Table 3. Alarm Mask Bits
REGISTER DY/DT 08H FFh F[0-9]h [0-9][0-9] [0-9][0-9] [0-9][0-9] [0-9][0-9] [0-9][0-9] [0-9][0-9] X X X X X X 0 1 ALARM REGISTER MASK BITS (BIT 7) AM4 1 1 1 1 1 1 0 0 AM3 1 1 1 1 1 0 0 0 AM2 1 1 1 1 0 0 0 0 AM1 1 1 1 0 0 0 0 0 ALARM RATE Alarm every 1/100th of a second Alarm when hundredths of seconds match Alarm when tenths, hundredths of seconds match Alarm when seconds, tenths, and hundredths of seconds match Alarm when minutes, seconds, tenths, and hundredths of seconds match Alarm when hours, minutes, seconds, tenths, and hundredths of seconds match Alarm when date, hours, minutes, seconds, tenths, and hundredths of seconds match Alarm when day, hours, minutes, seconds, tenths, and hundredths of seconds match
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the alarm-flag (AF) bit is set to logic 1. If the alarm-interrupt enable (AIE) is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT signal. Since the contents of register 08h are expected to normally contain a match value of 00-99 decimal, the codes F[0-9], and FF have been used to tell the part to mask the tenths or hundredths of seconds accordingly.
Power-Up/Down, Reset, and Pushbutton Reset Functions
A precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated that blocks read/write access to the device and forces the RST pin (DS1391/DS1393 only) low. When VCC returns to an in-tolerance condition, the internal power-fail signal is held active for tRST to allow the power supply to stabilize, and the RST (DS1391/ DS1393 only) pin is held low. If the EOSC bit is set to logic 1 (to disable the oscillator in battery-backup mode), the internal power-fail signal and the RST pin is kept active for tRST plus the startup time of the oscillator. The DS1391/DS1393 provide for a pushbutton switch to be connected to the RST output pin. When the DS1391/DS1393 are not in a reset cycle, it continuously monitors the RST signal for a low-going edge. If an edge is detected, the part debounces the switch by pulling the RST pin low and inhibits read/write access. After PBDB has expired, the part continues to monitor the RST line. If the line is still low, it continues to monitor the line looking for a rising edge. Upon detecting release, the part forces the RST pin low and holds it low for an additional PBDB.
DS1390/DS1391/DS1392/DS1393
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Special-Purpose Registers
The DS1390-DS1393 have three additional registers (control, status, and trickle charger) that control the RTC, alarms, square-wave output, and trickle charger. Control Register (0D/8Dh) (DS1390/DS1393 Only)
BIT 7 EOSC BIT 6 0 BIT 5 BBSQI BIT 4 RS2 BIT 3 RS1 BIT 2 INTCN BIT 1 0 BIT 0 AIE
Bit 7: Enable Oscillator (EOSC). When set to logic 0, this bit starts the oscillator. When this bit is set to logic 1, the oscillator is stopped whenever the device is powered by V BACKUP. The oscillator is always enabled when VCC is valid. This bit is enabled (logic 0) when VCC is first applied. Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to logic 1 enables the square wave or interrupt output when VCC is absent and the DS1390/DS1392/DS1393 are being powered by the V BACKUP pin. When BBSQI is logic 0, the SQW/INT pin (or SQW and INT pins) goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
Bit 2: Interrupt Control (INTCN). This bit controls the SQW/INT signal. When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers then activates the SQW/INT (provided the alarm is also enabled). The corresponding alarm flag is always set, regardless of the state of the INTCN bit. The INTCN bit is set to logic 0 when power is first applied. Bit 0: Alarm Interrupt Enable (AIE). When set to logic 1, this bit permits the alarm flag (AF) bit in the status register to assert SQW/INT (when INTCN = 1). When the AIE bit is set to logic 0 or INTCN is set to logic 0, the AF bit does not initiate the SQW/INT signal. The AIE bit is disabled (logic 0) when power is first applied.
Control Register (0D/8Dh) (DS1391 Only)
BIT 7 EOSC BIT 6 0 BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 0 BIT 0 X
Control bits used in the DS1390 become general-purpose, battery-backed, nonvolatile SRAM bits in the DS1391.
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
Control Register (0D/8Dh) (DS1392 Only)
BIT 7 EOSC BIT 6 0 BIT 5 BBSQI BIT 4 RS2 BIT 3 RS1 BIT 2 ESQW BIT 1 0 BIT 0 AIE
DS1390/DS1391/DS1392/DS1393
The INTCN bit used in the DS1390/DS1393 becomes the SQW pin-enable bit in the DS1392. This bit powers up a zero, making SQW active. Status Register (0E/8Eh)
BIT 7 OSF BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 AF
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time and may be used to judge the validity of the clock and calendar data. This bit is edge-triggered and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC and VBACKUP is insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Bit 6: Alarm Flag (AF). A logic 1 in the AF bit indicates that the time matched the alarm registers. If the AIE bit
is logic 1 and the INTCN bit is set to logic 1, the SQW/INT pin is also asserted. AF is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
Trickle-Charge Register (0F/8Fh)
The simplified schematic in Figure 9 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. If DS is 01, no diode is selected or if DS is 10, a diode is selected. The ROUT bits (bits 0 and 1) select the value of the resistor connected between V CC and VBACKUP. Table 5 shows the resistor selected by the resistor-select (ROUT) bits and the diode selected by the diode-select (DS) bits.
Table 5. Trickle-Charge Register
TCS3 X X X 1 1 1 1 1 1 0 TCS2 X X X 0 0 0 0 0 0 0 TCS1 X X X 1 1 1 1 1 1 0 TCS0 X X X 0 0 0 0 0 0 0 DS1 0 1 X 0 1 0 1 0 1 0 DS0 0 1 X 1 0 1 0 1 0 0 ROUT1 X X 0 0 0 1 1 1 1 0 ROUT0 X X 0 1 1 0 0 1 1 0 Disabled Disabled Disabled No diode, 250 resistor One diode, 250 resistor No diode, 2k resistor One diode, 2k resistor No diode, 4k resistor One diode, 4k resistor Initial default value--disabled FUNCTION
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
TRICKLE-CHARGE REGISTER (8Fh WRITE, 0Fh READ) BIT 7 TCS3 BIT 6 TCS2 BIT 5 TCS1 BIT 4 TCS0 BIT 3 DS1 BIT 2 DS0 BIT 1 ROUT1 BIT 0 ROUT0 TCS0-3 = TRICKLE-CHARGE SELECT DS0-1 = DIODE SELECT ROUT0-1 = RESISTOR SELECT
1 0F 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER
1 OF 2 SELECT
1 OF 3 SELECT R1 250
VCC
R2 2k R3 4k
VBACKUP
Figure 9. DS1390/DS1391 Programmable Trickle Charger
Table 6. SPI Pin Function
CS
MODE Disable
CSZ H
SCLK Input Disabled CPOL* = 1, SCLK Rising
SDI Input Disabled
SDO High Impedance
DATA LATCH (WRITE/INTERNAL STROBE) SHIFT DATA OUT (READ)
Write
L CPOL = 0, SCLK Falling CPOL = 1, SCLK Falling
Data Bit Latch
High Impedance
SCLK WHEN CPOL = 0 DATA LATCH (WRITE/INTERNAL STROBE) SHIFT DATA OUT (READ) SCLK WHEN CPOL = 1
Read
L CPOL = 0, SCLK Rising
X
Next Data Bit Shift**
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY. NOTE 2: CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER. NOTE 3: SDO REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE SHIFTED OUT DURING A READ.
*CPOL is the clock-polarity bit set in the control register of the host microprocessor. **SDO remains at high impedance until 8 bits of data are ready to be shifted out during a read.
Figure 10. Serial Clock as a Function of Microcontroller ClockPolarity Bit
The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 3.3V is applied to V CC and a super cap is connected to VBACKUP. Also, assume that the trickle charger has been enabled with a diode and resistor R2 between
VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2k 1.3mA As the super cap changes, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases.
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
CS
SCLK DIN W/R DOUT A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
Figure 11. SPI Single-Byte Write
CS
SCLK DIN W/R DOUT A6 A5 A4 A3 A2 A1 A0
HIGH IMPEDANCE D7 D6 D5 D4 D3 D2 D1 D0
Figure 12. SPI Single-Byte Read
SPI Serial-Data Bus
The DS1390/DS1391 provide a 4-wire SPI serial-data bus to communicate in systems with an SPI host controller. Both devices support single-byte and multiplebyte data transfers for maximum flexibility. The DIN and DOUT pins are the serial-data input and output pins, respectively. The CS input initiates and terminates a data transfer. The SCLK pin synchronizes data movement between the master (microcontroller) and the slave (DS1390/DS1391) devices. The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. Input data (DIN) is latched on the internal strobe edge and output data (DOUT) is shifted out on the shift edge (Figure 10). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight. Address and data bytes are shifted MSB first into the serial-data input (DIN) and out of the serial-data output (DOUT). Any transfer requires the address of the byte to specify a write or read, followed by one or more bytes of data. Data is transferred out of the DOUT pin for a read operation and into the DIN for a write operation (Figures 11 and 12).
The address byte is always the first byte entered after CS is driven low. The most significant bit (W/R) of this byte determines if a read or write takes place. If W/R is 0, one or more read cycles occur. If W/R is 1, one or more write cycles occur. Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven low, an address is written to the DS1390/DS1391. After the address, one or more data bytes can be written or read. For a singlebyte transfer, one byte is read or written and then CS is driven high. For a multiple-byte transfer, however, multiple bytes can be read or written after the address has been written. Each read or write cycle causes the RTC register address to automatically increment. Incrementing continues until the device is disabled. The address wraps to 00h after incrementing to 0Fh (during a read) and wraps to 80h after incrementing to 8Fh (during a write). Note, however, that an updated copy of the time is only loaded into the user-accessible copy upon the falling edge of CS. Reading the RTC registers in a continuous loop does not show the time advancing.
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
CS
SCLK
DIN WRITE ADDRESS BYTE DATA BYTE 0 DATA BYTE 1 DATA BYTE N
DIN ADDRESS BYTE READ
DOUT
HIGH-IMPEDANCE
DATA BYTE 0
DATA BYTE 1
DATA BYTE N
Figure 13. SPI Multiple-Byte Burst Transfer
CE
SCLK I/O
A0
A1
A2
A3
A4
A5
A6
W/R
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14. 3-Wire Single-Byte Read
CE
SCLK I/O
A0
A1
A2
A3
A4
A5
A6
W/R
D0
D1
D2
D3
D4
D5
D6
D7
Figure 15. 3-Wire Single-Byte Write 20 ____________________________________________________________________
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
3-Wire Serial-Data Bus
The DS1392/DS1393 provide a 3-wire serial-data bus, and support both single-byte and multiple-byte data transfers for maximum flexibility. The I/O pin is the serial-data input/output pin. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1392/DS1393) devices. Input data is latched on the SCLK rising edge and output data is shifted out on the SCLK falling edge. There is one clock for each bit transferred. Address and data bits are transferred in groups of eight. Address and data bytes are shifted LSB first into the I/O pin. Data is transferred out LSB first on the I/O pin for a read operation. The address byte is always the first byte entered after CE is driven high. The MSB (W/R) of this byte determines if a read or write takes place. If W/R is 0, one or more read cycles occur. If W/R is 1, one or more write cycles occur. Data transfers can be one byte at a time or in multiplebyte burst mode. After CE is driven high, an address is written to the DS1392/DS1393. After the address, one or more data bytes can be written or read. For a singlebyte transfer, one byte is read or written and then CE is driven low (Figure 14 and 15). For a multiple-byte transfer, however, multiple bytes can be read or written after the address has been written (Figure 16). Each read or write cycle causes the RTC register address to automatically increment. Incrementing continues until the device is disabled. The address wraps to 00h after
CE
DS1390/DS1391/DS1392/DS1393
SCLK I/O ADDRESS DATA BYTE BYTE 0 DATA BYTE 1 DATA BYTE N
Figure 16. 3-Wire Multiple-Byte Burst Transfer
incrementing to 0Fh (during a read) and wraps to 80h after incrementing to 8Fh (during a write). Note, however, that an updated copy of the time is only loaded into the user-accessible copy upon the rising edge of CE. Reading the RTC registers in a continuous loop does not show the time advancing.
Chip Information
TRANSISTOR COUNT: 11,525 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND
Thermal Information
Theta-JA: 180C/W Theta-JC: 41.9C/W
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Pin Configurations
TOP VIEW
X1 1 X2 2 VBACKUP 3 CS 4 GND 5
10 VCC
X1 X2 VBACKUP CS GND
1 2 3 4 5
10 VCC
DS1390
9 SQW/INT 8 SCLK 7 DOUT 6 DIN
DS1391
9 RST 8 SCLK 7 DOUT 6 DIN
SOP
SOP
X1 X2 VBACKUP CE GND
1 2 3 4 5
10 VCC
X1 X2 VBACKUP CE GND
1 2 3 4 5
10 VCC
DS1392
9 SQW 8 SCLK 7 I/O 6 INT
DS1393
9 SQW/INT 8 SCLK 7 I/O 6 RST
SOP
SOP
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger
Typical Operating Circuits
DS1390/DS1391/DS1392/DS1393
CRYSTAL VCC
VCC VCC
CRYSTAL
VCC
X1 CS
X2
VCC
X1 CS
X2
VCC
SQW/INT CPU SCLK DOUT DIN RST GND CPU
SCLK DOUT
DS1390
VBACKUP
DS1391
VBACKUP
DIN RST GND
CRYSTAL VCC
VCC
CRYSTAL
VCC
VCC X1 CE SQW CPU SCLK I/O CPU SCLK I/O X2 VCC X1 CE SQW/INT X2 VCC
DS1392
INT VBACKUP RST
DS1393
VBACKUP
RST GND
GND
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390/DS1391/DS1392/DS1393
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo).
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN A 0.043 A1 0.002 0.006 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H 0 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

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